diff options
| author | Jungseung Lee <js07.lee@samsung.com> | 2019-12-02 15:35:07 +0900 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-12-23 18:42:49 +0200 |
| commit | d1f4acb89c74926970a7733c7ac88d7561681bc7 (patch) | |
| tree | 741295cb29dda1b4618d3e9f25b86d0dc878432c /drivers/mtd/spi-nor/spi-nor.c | |
| parent | adf1092fa838e870813f2ac152973af311d8ae02 (diff) | |
mtd: spi-nor: Fix wrong TB selection of GD25Q256
For GD25Q256, wrong SR bit for top/bottom selection is being used.
Fix it to use appropriate bit.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'drivers/mtd/spi-nor/spi-nor.c')
| -rw-r--r-- | drivers/mtd/spi-nor/spi-nor.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 92b38157b38c..9ccde854f8ba 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -2395,7 +2395,8 @@ static const struct flash_info spi_nor_ids[] = { { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | + SPI_NOR_TB_SR_BIT6) .fixups = &gd25q256_fixups, }, |