diff options
| author | Boyuan Zhang <boyuan.zhang@amd.com> | 2020-04-02 13:28:07 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:12 -0400 |
| commit | d00b0fa90f4e524adb32a8b8d4702a16f671e946 (patch) | |
| tree | 7d77fbb055f912b64baf1e0be47f7f8f1eb88249 /drivers/gpu | |
| parent | 7055f4a353bbe0dfe99b0a5488644bbbeefe6a0a (diff) | |
drm/amdgpu: enable DPG mode for VCN3.0
Enable DPG mode for VCN3.0 by updating related flag.
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nv.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 7 |
2 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 936950fbafda..ef3f07dc89cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -726,6 +726,7 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_IH_CG | AMD_CG_SUPPORT_MC_LS; adev->pg_flags = AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_VCN_DPG | AMD_PG_SUPPORT_JPEG | AMD_PG_SUPPORT_ATHUB; adev->external_rev_id = adev->rev_id + 0x28; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 98ba6ddde823..875bdc877c3d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -254,7 +254,8 @@ static int vcn_v3_0_hw_init(void *handle) done: if (!r) - DRM_INFO("VCN decode and encode initialized successfully.\n"); + DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", + (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); return r; } @@ -278,7 +279,9 @@ static int vcn_v3_0_hw_fini(void *handle) ring = &adev->vcn.inst[i].ring_dec; - if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) + if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || + (adev->vcn.cur_state != AMD_PG_STATE_GATE && + RREG32_SOC15(VCN, i, mmUVD_STATUS))) vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); ring->sched.ready = false; |