diff options
author | Dave Airlie <airlied@redhat.com> | 2018-02-06 06:33:04 +1000 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2018-02-06 06:33:04 +1000 |
commit | b8a89f530f5692c70778c965f0bc8f5a61fbe703 (patch) | |
tree | ee8892ce84ffa5e9403a4a7fe6816248fb3306cb /drivers/gpu | |
parent | d6a841a4598bf3a08e68c520f38adc87d3bf4941 (diff) | |
parent | b515483e12b81da8cb62f1ff2461d6c29cf5115f (diff) |
Merge branch 'linux-4.16' of git://github.com/skeggsb/linux into drm-next
- initial kepler clock gating support
- atomic gamma handling fixes
- support for gp108 "secure boot" (enables acceleration, finally)
* 'linux-4.16' of git://github.com/skeggsb/linux:
drm/nouveau/clk: fix gcc-7 -Wint-in-bool-context warning
drm/nouveau/mmu: Fix trailing semicolon
drm/nouveau: Introduce NvPmEnableGating option
drm/nouveau: Add support for SLCG for Kepler2
drm/nouveau: Add support for BLCG on Kepler2
drm/nouveau: Add support for BLCG on Kepler1
drm/nouveau: Add support for basic clockgating on Kepler1
drm/nouveau/kms/nv50: fix handling of gamma since atomic conversion
drm/nouveau/kms/nv50: use INTERPOLATE_257_UNITY_RANGE LUT on newer chipsets
drm/nouveau/kms/nv50: use "low res" lut for indexed mode
drm/nouveau/kms/nv50: prepare for double-buffered LUTs
drm/nouveau/bo: add helper functions for handling pinned+mapped buffers
drm/nouveau/fbcon: add module parameter to select bits-per-pixel
drm/nouveau/secboot/gp108: implement on top of acr_r370
drm/nouveau/secboot/r370: implement support for booting LS SEC2 ucode
drm/nouveau/secboot/r370: move a bunch of r375 stuff to a new implementation
drm/nouveau: nouveau: use correct string length
drm/nouveau/drm/nouveau/mmu: fix odd_ptr_err.cocci warnings
drm/nouveau/pmu/fuc: don't use movw directly anymore
Diffstat (limited to 'drivers/gpu')
44 files changed, 2723 insertions, 1491 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h index adb78f7d083a..92be0e5269c6 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -75,6 +75,7 @@ int mcp89_fb_new(struct nvkm_device *, int, struct nvkm_fb **); int gf100_fb_new(struct nvkm_device *, int, struct nvkm_fb **); int gf108_fb_new(struct nvkm_device *, int, struct nvkm_fb **); int gk104_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int gk110_fb_new(struct nvkm_device *, int, struct nvkm_fb **); int gk20a_fb_new(struct nvkm_device *, int, struct nvkm_fb **); int gm107_fb_new(struct nvkm_device *, int, struct nvkm_fb **); int gm200_fb_new(struct nvkm_device *, int, struct nvkm_fb **); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h index 59f3ba551681..b57fe4ae93ba 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h @@ -60,6 +60,7 @@ int nvkm_secboot_reset(struct nvkm_secboot *, unsigned long); int gm200_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); int gm20b_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); int gp102_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); +int gp108_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); int gp10b_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h index b1ac47eb786e..9398d9f09339 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h @@ -46,6 +46,16 @@ enum nvkm_therm_attr_type { NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST = 17, }; +struct nvkm_therm_clkgate_init { + u32 addr; + u8 count; + u32 data; +}; + +struct nvkm_therm_clkgate_pack { + const struct nvkm_therm_clkgate_init *init; +}; + struct nvkm_therm { const struct nvkm_therm_func *func; struct nvkm_subdev subdev; @@ -85,17 +95,24 @@ struct nvkm_therm { int (*attr_get)(struct nvkm_therm *, enum nvkm_therm_attr_type); int (*attr_set)(struct nvkm_therm *, enum nvkm_therm_attr_type, int); + + bool clkgating_enabled; }; int nvkm_therm_temp_get(struct nvkm_therm *); int nvkm_therm_fan_sense(struct nvkm_therm *); int nvkm_therm_cstate(struct nvkm_therm *, int, int); +void nvkm_therm_clkgate_init(struct nvkm_therm *, + const struct nvkm_therm_clkgate_pack *); +void nvkm_therm_clkgate_enable(struct nvkm_therm *); +void nvkm_therm_clkgate_fini(struct nvkm_therm *, bool); int nv40_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int nv50_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int g84_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gt215_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gf119_therm_new(struct nvkm_device *, int, struct nvkm_therm **); +int gk104_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gm107_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gm200_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gp100_therm_new(struct nvkm_device *, int, struct nvkm_therm **); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h index 7b5cc5c73d20..be8e00b49cde 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.h +++ b/drivers/gpu/drm/nouveau/nouveau_bo.h @@ -105,4 +105,32 @@ nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) return ioptr; } +static inline void +nouveau_bo_unmap_unpin_unref(struct nouveau_bo **pnvbo) +{ + if (*pnvbo) { + nouveau_bo_unmap(*pnvbo); + nouveau_bo_unpin(*pnvbo); + nouveau_bo_ref(NULL, pnvbo); + } +} + +static inline int +nouveau_bo_new_pin_map(struct nouveau_cli *cli, u64 size, int align, u32 flags, + struct nouveau_bo **pnvbo) +{ + int ret = nouveau_bo_new(cli, size, align, flags, + 0, 0, NULL, NULL, pnvbo); + if (ret == 0) { + ret = nouveau_bo_pin(*pnvbo, flags, true); + if (ret == 0) { + ret = nouveau_bo_map(*pnvbo); + if (ret == 0) + return ret; + nouveau_bo_unpin(*pnvbo); + } + nouveau_bo_ref(NULL, pnvbo); + } + return ret; +} #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_crtc.h b/drivers/gpu/drm/nouveau/nouveau_crtc.h index b7a18fbee6dc..366acb928f57 100644 --- a/drivers/gpu/drm/nouveau/nouveau_crtc.h +++ b/drivers/gpu/drm/nouveau/nouveau_crtc.h @@ -60,7 +60,6 @@ struct nouveau_crtc { } cursor; struct { - struct nouveau_bo *nvbo; int depth; } lut; diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index ee5d1dc2eaf5..85c1f10bc2b6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -56,6 +56,10 @@ MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration"); int nouveau_nofbaccel = 0; module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400); +MODULE_PARM_DESC(fbcon_bpp, "fbcon bits-per-pixel (default: auto)"); +static int nouveau_fbcon_bpp; +module_param_named(fbcon_bpp, nouveau_fbcon_bpp, int, 0400); + static void nouveau_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { @@ -488,7 +492,7 @@ nouveau_fbcon_init(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_fbdev *fbcon; - int preferred_bpp; + int preferred_bpp = nouveau_fbcon_bpp; int ret; if (!dev->mode_config.num_crtc || @@ -512,13 +516,15 @@ nouveau_fbcon_init(struct drm_device *dev) if (ret) goto fini; - if (drm->client.device.info.ram_size <= 32 * 1024 * 1024) - preferred_bpp = 8; - else - if (drm->client.device.info.ram_size <= 64 * 1024 * 1024) - preferred_bpp = 16; - else - preferred_bpp = 32; + if (preferred_bpp != 8 && preferred_bpp != 16 && preferred_bpp != 32) { + if (drm->client.device.info.ram_size <= 32 * 1024 * 1024) + preferred_bpp = 8; + else + if (drm->client.device.info.ram_size <= 64 * 1024 * 1024) + preferred_bpp = 16; + else + preferred_bpp = 32; + } /* disable all the possible outputs/crtcs before entering KMS mode */ if (!drm_drv_uses_atomic_modeset(dev)) diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index b22c37bde13f..dd8d4352ed99 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -137,8 +137,10 @@ struct nv50_head_atom { } mode; struct { + bool visible; u32 handle; u64 offset:40; + u8 mode:4; } lut; struct { @@ -192,6 +194,7 @@ struct nv50_head_atom { union { struct { + bool ilut:1; bool core:1; bool curs:1; }; @@ -200,6 +203,7 @@ struct nv50_head_atom { union { struct { + bool ilut:1; bool core:1; bool curs:1; bool view:1; @@ -660,6 +664,10 @@ nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp, struct nv50_head { struct nouveau_crtc base; + struct { + struct nouveau_bo *nvbo[2]; + int next; + } lut; struct nv50_ovly ovly; struct nv50_oimm oimm; }; @@ -1795,6 +1803,54 @@ nv50_head_lut_clr(struct nv50_head *head) } static void +nv50_head_lut_load(struct drm_property_blob *blob, int mode, + struct nouveau_bo *nvbo) +{ + struct drm_color_lut *in = (struct drm_color_lut *)blob->data; + void __iomem *lut = (u8 *)nvbo_kmap_obj_iovirtual(nvbo); + const int size = blob->length / sizeof(*in); + int bits, shift, i; + u16 zero, r, g, b; + + /* This can't happen.. But it shuts the compiler up. */ + if (WARN_ON(size != 256)) + return; + + switch (mode) { + case 0: /* LORES. */ + case 1: /* HIRES. */ + bits = 11; + shift = 3; + zero = 0x0000; + break; + case 7: /* INTERPOLATE_257_UNITY_RANGE. */ + bits = 14; + shift = 0; + zero = 0x6000; + break; + default: + WARN_ON(1); + return; + } + + for (i = 0; i < size; i++) { + r = (drm_color_lut_extract(in[i]. red, bits) + zero) << shift; + g = (drm_color_lut_extract(in[i].green, bits) + zero) << shift; + b = (drm_color_lut_extract(in[i]. blue, bits) + zero) << shift; + writew(r, lut + (i * 0x08) + 0); + writew(g, lut + (i * 0x08) + 2); + writew(b, lut + (i * 0x08) + 4); + } + + /* INTERPOLATE modes require a "next" entry to interpolate with, + * so we replicate the last entry to deal with this for now. + */ + writew(r, lut + (i * 0x08) + 0); + writew(g, lut + (i * 0x08) + 2); + writew(b, lut + (i * 0x08) + 4); +} + +static void nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh) { struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; @@ -1802,18 +1858,18 @@ nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((push = evo_wait(core, 7))) { if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); - evo_data(push, 0xc0000000); + evo_data(push, 0x80000000 | asyh->lut.mode << 30); evo_data(push, asyh->lut.offset >> 8); } else if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); - evo_data(push, 0xc0000000); + evo_data(push, 0x80000000 | asyh->lut.mode << 30); evo_data(push, asyh->lut.offset >> 8); evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); evo_data(push, asyh->lut.handle); } else { evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4); - evo_data(push, 0x83000000); + evo_data(push, 0x80000000 | asyh->lut.mode << 24); evo_data(push, asyh->lut.offset >> 8); evo_data(push, 0x00000000); evo_data(push, 0x00000000); @@ -1896,7 +1952,7 @@ nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh) static void nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y) { - if (asyh->clr.core && (!asyh->set.core || y)) + if (asyh->clr.ilut && (!asyh->set.ilut || y)) nv50_head_lut_clr(head); if (asyh->clr.core && (!asyh->set.core || y)) nv50_head_core_clr(head); @@ -1909,7 +1965,15 @@ nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) { if (asyh->set.view ) nv50_head_view (head, asyh); if (asyh->set.mode ) nv50_head_mode (head, asyh); - if (asyh->set.core ) nv50_head_lut_set (head, asyh); + if (asyh->set.ilut ) { + struct nouveau_bo *nvbo = head->lut.nvbo[head->lut.next]; + struct drm_property_blob *blob = asyh->state.gamma_lut; + if (blob) + nv50_head_lut_load(blob, asyh->lut.mode, nvbo); + asyh->lut.offset = nvbo->bo.offset; + head->lut.next ^= 1; + nv50_head_lut_set(head, asyh); + } if (asyh->set.core ) nv50_head_core_set(head, asyh); if (asyh->set.curs ) nv50_head_curs_set(head, asyh); if (asyh->set.base ) nv50_head_base (head, asyh); @@ -2044,6 +2108,37 @@ nv50_head_atomic_check_view(struct nv50_head_atom *armh, } static void +nv50_head_atomic_check_lut(struct nv50_head *head, + struct nv50_head_atom *armh, + struct nv50_head_atom *asyh) +{ + struct nv50_disp *disp = nv50_disp(head->base.base.dev); + + /* An I8 surface without an input LUT makes no sense, and + * EVO will throw an error if you try. + * + * Legacy clients actually cause this due to the order in + * which they call ioctls, so we will enable the LUT with + * whatever contents the buffer already contains to avoid + * triggering the error check. + */ + if (!asyh->state.gamma_lut && asyh->base.cpp != 1) { + asyh->lut.handle = 0; + asyh->clr.ilut = armh->lut.visible; + return; + } + + if (disp->disp->oclass < GF110_DISP) { + asyh->lut.mode = (asyh->base.cpp == 1) ? 0 : 1; + asyh->set.ilut = true; + } else { + asyh->lut.mode = 7; + asyh->set.ilut = asyh->state.color_mgmt_changed; + } + asyh->lut.handle = disp->mast.base.vram.handle; +} + +static void nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh) { struct drm_display_mode *mode = &asyh->state.adjusted_mode; @@ -2128,6 +2223,11 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) if (asyh->state.mode_changed) nv50_head_atomic_check_mode(head, asyh); + if (asyh->state.color_mgmt_changed || + asyh->base.cpp != armh->base.cpp) + nv50_head_atomic_check_lut(head, armh, asyh); + asyh->lut.visible = asyh->lut.handle != 0; + if (asyc) { if (asyc->set.scaler) nv50_head_atomic_check_view(armh, asyh, asyc); @@ -2143,7 +2243,8 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) asyh->core.w = asyh->base.w; asyh->core.h = asyh->base.h; } else - if ((asyh->core.visible = asyh->curs.visible)) { + if ((asyh->core.visible = asyh->curs.visible) || + (asyh->core.visible = asyh->lut.visible)) { /*XXX: We need to either find some way of having the * primary base layer appear black, while still * being able to display the other layers, or we @@ -2161,11 +2262,10 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) asyh->core.layout = 1; asyh->core.block = 0; asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4; - asyh->lut.handle = disp->mast.base.vram.handle; - asyh->lut.offset = head->base.lut.nvbo->bo.offset; asyh->set.base = armh->base.cpp != asyh->base.cpp; asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp; } else { + asyh->lut.visible = false; asyh->core.visible = false; asyh->curs.visible = false; asyh->base.cpp = 0; @@ -2189,8 +2289,10 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) asyh->clr.curs = true; } } else { + asyh->clr.ilut = armh->lut.visible; asyh->clr.core = armh->core.visible; asyh->clr.curs = armh->curs.visible; + asyh->set.ilut = asyh->lut.visible; asyh->set.core = asyh->core.visible; asyh->set.curs = asyh->curs.visible; } @@ -2200,47 +2302,11 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) return 0; } -static void -nv50_head_lut_load(struct drm_crtc *crtc) -{ - struct nv50_disp *disp = nv50_disp(crtc->dev); - struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); - void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); - u16 *r, *g, *b; - int i; - - r = crtc->gamma_store; - g = r + crtc->gamma_size; - b = g + crtc->gamma_size; - - for (i = 0; i < 256; i++) { - if (disp->disp->oclass < GF110_DISP) { - writew((*r++ >> 2) + 0x0000, lut + (i * 0x08) + 0); - writew((*g++ >> 2) + 0x0000, lut + (i * 0x08) + 2); - writew((*b++ >> 2) + 0x0000, lut + (i * 0x08) + 4); - } else { - /* 0x6000 interferes with the 14-bit color??? */ - writew((*r++ >> 2) + 0x6000, lut + (i * 0x20) + 0); - writew((*g++ >> 2) + 0x6000, lut + (i * 0x20) + 2); - writew((*b++ >> 2) + 0x6000, lut + (i * 0x20) + 4); - } - } -} - static const struct drm_crtc_helper_funcs nv50_head_help = { .atomic_check = nv50_head_atomic_check, }; -static int -nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, - uint32_t size, - struct drm_modeset_acquire_ctx *ctx) -{ - nv50_head_lut_load(crtc); - return 0; -} - static void nv50_head_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) @@ -2296,17 +2362,15 @@ nv50_head_reset(struct drm_crtc *crtc) static void nv50_head_destroy(struct drm_crtc *crtc) { - struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct nv50_disp *disp = nv50_disp(crtc->dev); struct nv50_head *head = nv50_head(crtc); + int i; nv50_dmac_destroy(&head->ovly.base, disp->disp); nv50_pioc_destroy(&head->oimm.base); - nouveau_bo_unmap(nv_crtc->lut.nvbo); - if (nv_crtc->lut.nvbo) - nouveau_bo_unpin(nv_crtc->lut.nvbo); - nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); + for (i = 0; i < ARRAY_SIZE(head->lut.nvbo); i++) + nouveau_bo_unmap_unpin_unref(&head->lut.nvbo[i]); drm_crtc_cleanup(crtc); kfree(crtc); @@ -2315,7 +2379,7 @@ nv50_head_destroy(struct drm_crtc *crtc) static const struct drm_crtc_funcs nv50_head_func = { .reset = nv50_head_reset, - .gamma_set = nv50_head_gamma_set, + .gamma_set = drm_atomic_helper_legacy_gamma_set, .destroy = nv50_head_destroy, .set_config = drm_atomic_helper_set_config, .page_flip = drm_atomic_helper_page_flip, @@ -2333,7 +2397,7 @@ nv50_head_create(struct drm_device *dev, int index) struct nv50_base *base; struct nv50_curs *curs; struct drm_crtc *crtc; - int ret; + int ret, i; head = kzalloc(sizeof(*head), GFP_KERNEL); if (!head) @@ -2355,22 +2419,14 @@ nv50_head_create(struct drm_device *dev, int index) drm_crtc_helper_add(crtc, &nv50_head_help); drm_mode_crtc_set_gamma_size(crtc, 256); - ret = nouveau_bo_new(&drm->client, 8192, 0x100, TTM_PL_FLAG_VRAM, - 0, 0x0000, NULL, NULL, &head->base.lut.nvbo); - if (!ret) { - ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true); - if (!ret) { - ret = nouveau_bo_map(head->base.lut.nvbo); - if (ret) - nouveau_bo_unpin(head->base.lut.nvbo); - } + for (i = 0; i < ARRAY_SIZE(head->lut.nvbo); i++) { + ret = nouveau_bo_new_pin_map(&drm->client, 1025 * 8, 0x100, + TTM_PL_FLAG_VRAM, + &head->lut.nvbo[i]); if (ret) - nouveau_bo_ref(NULL, &head->base.lut.nvbo); + goto out; } - if (ret) - goto out; - /* allocate overlay resources */ ret = nv50_oimm_create(device, disp->disp, index, &head->oimm); if (ret) @@ -4350,7 +4406,6 @@ nv50_display_init(struct drm_device *dev) { struct drm_encoder *encoder; struct drm_plane *plane; - struct drm_crtc *crtc; u32 *push; push = evo_wait(nv50_mast(dev), 32); @@ -4369,10 +4424,6 @@ nv50_display_init(struct drm_device *dev) } } - drm_for_each_crtc(crtc, dev) { - nv50_head_lut_load(crtc); - } - drm_for_each_plane(plane, dev) { struct nv50_wndw *wndw = nv50_wndw(plane); if (plane->funcs != &nv50_wndw) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 00eeaaffeae5..073534ab6911 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -28,6 +28,7 @@ #include <core/option.h> #include <subdev/bios.h> +#include <subdev/therm.h> static DEFINE_MUTEX(nv_devices_mutex); static LIST_HEAD(nv_devices); @@ -1682,7 +1683,7 @@ nve4_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk104_pmu_new, - .therm = gf119_therm_new, + .therm = gk104_therm_new, .timer = nv41_timer_new, .top = gk104_top_new, .volt = gk104_volt_new, @@ -1721,7 +1722,7 @@ nve6_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk104_pmu_new, - .therm = gf119_therm_new, + .therm = gk104_therm_new, .timer = nv41_timer_new, .top = gk104_top_new, .volt = gk104_volt_new, @@ -1760,7 +1761,7 @@ nve7_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk104_pmu_new, - .therm = gf119_therm_new, + .therm = gk104_therm_new, .timer = nv41_timer_new, .top = gk104_top_new, .volt = gk104_volt_new, @@ -1811,7 +1812,7 @@ nvf0_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gf100_devinit_new, - .fb = gk104_fb_new, + .fb = gk110_fb_new, .fuse = gf100_fuse_new, .gpio = gk104_gpio_new, .i2c = gk104_i2c_new, @@ -1824,7 +1825,7 @@ nvf0_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk110_pmu_new, - .therm = gf119_therm_new, + .therm = gk104_therm_new, .timer = nv41_timer_new, .top = gk104_top_new, .volt = gk104_volt_new, @@ -1849,7 +1850,7 @@ nvf1_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gf100_devinit_new, - .fb = gk104_fb_new, + .fb = gk110_fb_new, .fuse = gf100_fuse_new, .gpio = gk104_gpio_new, .i2c = gk104_i2c_new, @@ -1862,7 +1863,7 @@ nvf1_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk110_pmu_new, - .therm = gf119_therm_new, + .therm = gk104_therm_new, .timer = nv41_timer_new, .top = gk104_top_new, .volt = gk104_volt_new, @@ -1887,7 +1888,7 @@ nv106_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gf100_devinit_new, - .fb = gk104_fb_new, + .fb = gk110_fb_new, .fuse = gf100_fuse_new, .gpio = gk104_gpio_new, .i2c = gk104_i2c_new, @@ -1900,7 +1901,7 @@ nv106_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk208_pmu_new, - .therm = gf119_therm_new, + .therm = gk104_therm_new, .timer = nv41_timer_new, .top = gk |