summaryrefslogtreecommitdiffstats
path: root/drivers/gpu
diff options
context:
space:
mode:
authorKenneth Feng <kenneth.feng@amd.com>2020-03-27 14:17:41 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-07-01 01:59:12 -0400
commit31cb0dd9a29195a9e9bc3030de87887865d6ffc7 (patch)
tree13fa13b4ec033ec33ff02ecd02e448d31aee36f0 /drivers/gpu
parent846938c223dab849d039ec24392190a383077765 (diff)
drm/amd/powerplay: enable GPO
GPO is graphics power optimizer. SMU calculates the 16 gfxclk V/F points according to the CU numbers and memory activity.RLC picks one of them according to the memory speed requirements for the data transmission. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu_types.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c1
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
index 3efadf2cff9c..dff2295705be 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -260,6 +260,7 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(MMHUB_PG), \
__SMU_DUMMY_MAP(ATHUB_PG), \
__SMU_DUMMY_MAP(APCC_DFLL), \
+ __SMU_DUMMY_MAP(DPM_GFX_GPO), \
__SMU_DUMMY_MAP(WAFL_CG),
#undef __SMU_DUMMY_MAP
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 8fb08cae5c24..9dbf29e96312 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -126,6 +126,7 @@ static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] =
static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
FEA_MAP(DPM_PREFETCHER),
FEA_MAP(DPM_GFXCLK),
+ FEA_MAP(DPM_GFX_GPO),
FEA_MAP(DPM_UCLK),
FEA_MAP(DPM_SOCCLK),
FEA_MAP(DPM_MP0CLK),