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authorLikun Gao <Likun.Gao@amd.com>2020-03-24 15:25:40 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-07-01 01:59:11 -0400
commit3059ec1c3c5cc34505c141c398355132021f5184 (patch)
treef4359e1d7e98dc6ee71fb84f5e77ad07028e0b74 /drivers/gpu/drm/amd/powerplay
parentcf06331fed5bffa10e04e15f5c26a8836dbc38d5 (diff)
drm/amd/powerplay: add function to get power limit for sienna_cichlid
Add function to get pptable power limit for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay')
-rw-r--r--drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 2db4b3fb0cf9..2843e1be4289 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1501,6 +1501,12 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
return ret;
}
+static uint32_t sienna_cichlid_get_pptable_power_limit(struct smu_context *smu)
+{
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
+ return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
+}
+
static int sienna_cichlid_get_power_limit(struct smu_context *smu,
uint32_t *limit,
bool cap)
@@ -2335,6 +2341,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ .get_pptable_power_limit = sienna_cichlid_get_pptable_power_limit,
};
void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)