diff options
| author | Konrad Dybcio <konradybcio@gmail.com> | 2020-07-26 13:12:01 +0200 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2020-07-31 06:46:17 -0700 |
| commit | 694dd304cc294b69db7191cec1d83e5a29c6a4b0 (patch) | |
| tree | 9587ebd396d81a7f95cab5c077c3e6302cabbe8b /Documentation/devicetree | |
| parent | 66ffb9150b00f3fdf50d08153df36d6ea052dbd4 (diff) | |
drm/msm/dsi: Add phy configuration for SDM630/636/660
These SoCs make use of the 14nm phy, but at different
addresses than other 14nm units.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/display/msm/dsi.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index af95586c898f..7884fd7a85c1 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -87,6 +87,7 @@ Required properties: * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" * "qcom,dsi-phy-14nm" + * "qcom,dsi-phy-14nm-660" * "qcom,dsi-phy-10nm" * "qcom,dsi-phy-10nm-8998" - reg: Physical base address and length of the registers of PLL, PHY. Some |