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authorRupert Rutledge <eosis2 [at] gmail.com>2020-05-09 17:23:43 +0100
committerRupert Rutledge <eosis2 [at] gmail.com>2020-05-09 17:23:43 +0100
commit53b80c7175a42dc5dd4b6b3ead65fc107c2f532e (patch)
tree8a913b0b60da03d4763afad5ac63225340a80482
parent0122bf351aefe55c568d24097b3f7eaa259ef041 (diff)
Fix silly issue with altering logic
- Needed to set max number of columns to 3.
-rw-r--r--src/display/components/total_bandwidth.rs5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/display/components/total_bandwidth.rs b/src/display/components/total_bandwidth.rs
index c9a9676..8a16b3e 100644
--- a/src/display/components/total_bandwidth.rs
+++ b/src/display/components/total_bandwidth.rs
@@ -87,7 +87,10 @@ impl<'a> HeaderDetails<'a> {
fn header_parts(&self, rect: Rect) -> Vec<Rect> {
const MAX_BANDWIDTH_STRING_LENGTH: u16 = 31;
- let number_of_columns = rect.width / MAX_BANDWIDTH_STRING_LENGTH;
+ let number_of_columns = *[3, rect.width / MAX_BANDWIDTH_STRING_LENGTH]
+ .iter()
+ .min()
+ .unwrap();
let constraints: Vec<Constraint> = (0..number_of_columns)
.map(|_| Constraint::Percentage(100 / number_of_columns))
.collect();